DSP synthesis startup Algotochip emerges from stealth mode

Algotochip claims to be able to create DSP designs directly from C-language algorithm descriptions.

Algotochip, a Silicon Valley-based startup focused on the synthesis of Digital Signal Processor (DSP) Systems on a Chip (SoCs) directly from C-language algorithms, emerged from stealth mode at the GlobalPress Electronics Summit in Santa Cruz, CA today.


In his presentation, Algotochip CTO Satish Padmanabhan acknowledged that the long-held notion of an ESL tool that could synthesize an entire system written in 'C' is not realistic. However, by constraining their solution to sequential processes for executing DSP algorithms, Algotochip can directly realize a system and generate all aspects of the solution, including the software, firmware, and the Register-Transfer Level (RTL) description and GDSII physical layout.


Padmanabhan said that he does not classify his company as an Electronic Design Automation (EDA) provider, but as an R&D partner for his customers. The customer does not need to use nor need to have any knowledge of Algotochip's proprietary technology and tools. Customers just provide a textual system specification, and the executable C-language algorithm, along with a set of test vectors as inputs to the Algotochip process.

Algotochip then works with the customer to understand the functions of their algorithm, perform the necessary optimizations, and then generate a design for the target implementation that is 100% license free and owned by the customer.


The synthesized design includes a Software Developer Kit (SDK), which includes a compiler, assembler, linker and a cycle-accurate simulator. Algotochip also provides the necessary firmware, and hardware, including the architecture with synthesizable RTL and  physical implementation in GDSII format. According to Padmanabhan, the entire process can be completed in just 8-16 weeks.


For DSP designs, he said that the methodology can automatically determine the parallelization that is required to execute the algorithm in hardware. The tools will determine where the hardware-software partitioning calls for insertion of hardware accelerators, such as LTE Turbo encoding, versus synthesis of a programmable processor for less performance-intensive tasks. However, the target platforms for Algotochip's solution are currently limited to ASIC implementation. Algotochip is working on a solution for FPGAs, says Padmanabhan.


As part of the announcement at the GlobalPress summit, Algotochip announced that they had delivered a SoC silicon solution to LTE PHY and protocol stack provider mimoOn, for their mi!MobilePHY reference chain. The companies say that the design process, with generation of complete SoC GDSII for mimoOn’s C-code, was completed in 12 weeks, for TSMC90GOD and TSMC40G processes.


Padmanabhan, who was the Chief Architect of 10Gigabit Ethernet and 10Gigabit SONET products at Riverstone Networks and Lucent Technologies, says that Algotochip has been funded by the venture arm of a "large corporation". He expects that the investor's identity will be revealed "in the next 2 or 3 months".