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| CEVA's TeakLite-4 is the company's 4th generation DSP architecture, optimized for voice and High-Definition audio applications. |
CEVA, Inc., licensor of Silicon Intellectual Property (SIP) DSP cores, has announced development of TeakLite-4, the company's 4th generation DSP architecture for audio and voice applications, and the 2nd generation of the company's 32-bit architecture. Moshe Sheier, Product Manager for Voice and Audio Solutions at CEVA, says that TeakLite-4 is capable of reducing power by up to 30% from TeakLite-III, due to incorporation of the latest version of CEVA's Power Scaling Unit (PSU 2.0), which the company introduced in the XC4000 architecture for wireless baseband applications earlier this year.
CEVA will initially offer TeakLite-4 in four different configurations, starting with the low-power TL410/411 in Q2, which are targeted for integration in standalone DSP chips. The smallest device in the family, the TL410, is 25% smaller than TeakLite-III, says Sheier, utilizing a less than 100K gate core. The TL410 incorporates a single 32x32-bit Multiplier-Accumulator (MAC), and the TL411 (140K gates) provides dual 32x32-bit MACs. Both versions of TeakLite-4 incorporate a 64-bit data memory bandwidth interface for local DSP memory.
The high-performance CEVA TL420/421 (190K/230K gates), which will be available in Q3, are targeted for integration in heterogeneous application processors, combining DSP with a CPU. Targeted markets are for mobile, Digital TV (DTV), and Set-Top Box (STB) applications. The TL420/421 provide similar choices of single or dual 32x32b MACs, with the addition of an optional memory subsystem for interfacing to cache controllers, and a master/slave ARM Advanced eXtensible Interface (AXI). In a TSMC 28nm HPM process, the TeakLite-4 can operate with up to a 1.5GHz clock frequency.
Sheier says that CEVA customers can optimize the TeakLite-4 DSP architecture for their requirements, choosing either one, two, or four 32x32-bit MACs, or two or four 16x16-bit MACs, and an optional Floating Point Unit (FPU). For high performance applications, such as in High Definition audio codecs, and wideband voice and audio post-processing, TeakLite-4 can execute up to four 32x32-bit (or 16x16-bit) MAC operations per cycle. CEVA also supports 16x32 or 24x24-bit operations.
Customers can differentiate their end products by adding their own accelerators, and by adding their own extensions to CEVA's audio/voice optimized Instruction Set Architecture (ISA). Users can also employ optional ISA components, such as CEVA's bit-stream processing acceleration.
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