Competition in 100G Ethernet: Intel partner Achronix vs. Broadcom, Altera and Xilinx

Achronix is targeting the Speedster22i FPGA at high-performance communication markets, such as 100G Ethernet

Suppliers of Field-Programmable Gate Arrays (FPGAs) frequently attempt to differentiate their products from Application-Specific Standard Products (ASSPs), by citing the performance advantages and flexibility of programmable logic. The parallel processing and hardware acceleration features of FPGA fabrics, and their high-performance Input-Output (I/O) interfaces, are often used as a complement to software-programmable ASSPs, particularly in Digital Signal Processing (DSP) applications. However, that flexibility comes at a cost, as FPGAs are much less silicon-area efficient than purpose-built fixed-function designs.

For FPGA vendors, the answer has been to add hardened cores to their devices, essentially producing hybrids that mix programmable and fixed functions on the same chip. Standard I/O interfaces, such as the Peripheral Component Interconnect Express (PCIe), have been prime candidates for such "hardening". The new generation of FPGA Systems on a Chip (SoCs) go one step further, bringing embedded ARM Cortex-A9 cores onto the chip alongside programmable logic.

In an announcement on April 24,  FPGA supplier Achronix Semiconductor described their intent to take this FPGA hybrid approach into the high performance communications market, with their line of Speedster22i FPGAs. Achronix CEO Robert Blake says that the '22' represents the 22nm manufacturing process node, and the 'i' stands for Intel - who is supplying their Tri-Gate FinFET process, and has also partnered in the engineering of Speedster. Blake says that Intel provided design assistance for core Intellectual Property (IP) building blocks in Speedster, such as the I/O, embedded memory and Phase-Locked Loops (PLLs), and is also supplying the high pin-count packaging, test and qualification services.

In the architecture of Speedster, Achronix and Intel have produced a design that is highly targeted to applications such as 100 Gigabit Ethernet (100GbE), by hardening the Media Access Controller (MAC) and Serializer-Deserializer (SERDES), as well as the PCIe, Interlaken, and DDR-3 memory interfaces. Interlaken is an interconnect protocol, originally designed by Cisco and Cortina Systems, that is optimized for high bandwidth packet transfers.

Blake says that by dedicating functions narrowly for their target communications and test markets, Speedster22i is positioned more closely to the $11B ASIC/ASSP market, at half the cost and power of other high-density 28nm FPGA solutions. This means that the competition is not just Altera and Xilinx however, as this narrow focus also places Achronix more directly up against network ASSP vendors, such as Broadcom.  In a coincidence of announcements, Broadcom detailed their own new highly-integrated device for 100GbE - the BCM88030 network processor, also on April 24 at the GlobalPress Electronics Summit in Santa Cruz, CA.

The first version of the Speedster22i family that will be available is the HD1000. Achronix is planning to begin shipping engineering samples in Q3 2012, and is offering an early access program to help customers migrate from traditional FPGAs to Speedster 22i. The early access program will include PCIe evaluation boards, onsite training and technical support. According to Blake, Achronix will also offer reference starting point designs for the evaluation board, in the Q3 time frame.

The HD1000 will vie with the Xilinx multi-chip 2.5D Virtex-7 2000T for the title of the industry's highest capacity FPGA, with over 1 million effective Look-Up Tables (LUTs) and 84Mb of embedded RAM. Only 700,000 of the HD1000 LUTs are programmable, however, as Achronix attributes the rest to the equivalent functionality in the hard core embedded IP blocks.

Achronix is also developing a Speedster22i HP family for higher performance, with the Achronix picoPIPE self-timed architecture, and operation up to 1.5 GHz. The Speedster22i HP FPGAs will comprise two models, the HP360 and HP560, targeted for feed forward data flow and DSP applications. Achronix is planning availability for the HP family in Q1 2013. The larger HP560 will provide 250 thousand LUTs, and 64 Mb of embedded RAM, along with the same hard IP cores of the HD1000.

In an example application, the Achronix HD1000 could be used to implement a 200Gbps Ethernet line card

Broadcom 100GbE Network Processor - Eliminating the FPGA

Achronix's Blake described an example application for the Speedster HD1000, in a 200Gbps Ethernet line card. The HD1000 could provide dual 100GbE MACs, to connect to off-chip C form-factor pluggable (CFP) optical transceivers. On-chip Interlaken interfaces can provide the connection to the backplane switch fabric interface.The FPGA's programmable logic could then be used to provide packet classification, and queuing functions, to offload a network processor.

In contrast, Broadcom's development of the BCM88030 is designed to eliminate the need for external FPGAs, off-chip 10/40/100GbE MACs, and the external physical interface (PHY) on ethernet line cards. Dan Harding, Senior Director of Product Marketing at Broadcom, says that the BCM88030 provides the industry's first full-duplex 100GbE network processor for Carrier Ethernet applications.

The BCM88030 is a family of 40nm network processors, integrating 64 hardware multi-threaded cores operating at a 1GHz clock frequency, which Broadcom has optimized for network processing. Harding says that the design enables processing of 32 packets per core, or 2K packets at a time on a single chip, delivering 300M packets/sec performance. Broadcom integrated 40G and 100G MACs directly into the chip with 24 10G SERDES.  The BCM88030 replace several chips in current designs, including an external FPGA used for Operations, Administration and Management (OAM) functions, and an IEEE-1588 Precision Timing Protocol Processor. Broadcom integrates their own engines for classification, lookups, policing, and statistics, to offload the processor cores.

Broadcom also supplies a Software Developer Kit (SDK) and source code with the BCM88030, along with a simulation model and debugger.The software supports Layer-2 or Layer-3 packet forwarding operations, Multi-protocol Label Switching (MPLS) and Transport Profile (MPLS-TP) functions, OAM, Timing and Metering.

The BCM88030 family includes a Broadcom proprietary algorithmic look up engine, which allows the use of low cost DDR-3 DRAM for Layer 2, IPv4 and IPv6 tables. Harding says that complex Access Control List (ACL) lookups, which may require matching on fields with wild cards, are often required for implementation of network security rules. Users can expand on the BCM88030 built-in algorithmic capability, with the NL566xx Knowledge-Based Processors (KBP), which came with Broadcom's acquisition of NetLogic Microsystems earlier this year.

In Broadcom's Ethernet line card example, four BCM88038 devices connect directly to external optical transceiver modules, and a switch fabric interface, to provide a total maximum of 400Gbps throughput, twice the data capacity of the Achronix example. Besides the 100Gbps BCM88038, the Broadcom product family will include a 50Gbps BCM88034, and the 24Gbps BCM88032. Broadcom says that each of the devices are now sampling, and they are targeting production volume for the second half of 2012.

Xilinx develops next-generation tool suite for FPGA design - Vivado

Xilinx's Vivado IDE will provide a new cockpit for designing FPGAs, from ESL to simulation, debug, and place & route

  

(note: typographical errors corrected and updates from Xilinx added on 4/25/12)
Xilinx, Inc. has announced a successor to their ISE FPGA design tools, the Vivado Design Suite, which the company is targeting at silicon intellectual property (SIP) and system-centric design flows. Xilnx is positioning the new tool set as a solution for what they say will be the next-generation of "All Programmable Devices", spanning the traditional programmable logic and I/O features of FPGAs, as well as integration of Analog/Mixed-Signal (AMS) blocks, stacked interconnect for 3D ICs, and embedded ARM processing systems in FPGA SoCs.

The Vivado Design Suite provides an Integrated Design Environment (IDE) with a new set of system-to-IC level tools, built with a shared data model and a common debug environment. Xilinx is supporting standards in Vivado which the semiconductor industry has previously developed for SoC implementation, including ARM's Advanced Microntroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) interconnect specification, Accellera's IP-XACT IP packaging metadata standard, IEEE P1735 methods for IP security and rights management, Tool Command Language (Tcl) scripting, and the Synopsys Design Constraints (SDC) format.

Physical Implementation in Vivado, inherited from HierDesign

For Vivado, Xilinx built upon the hierarchical floor planning capabilities of the "PlanAhead" tool, which came with their 2004 acquisition of Hier Design, to construct an environment for running every step in a FPGA design flow. Xilinx adopted the PlanAhead database format as the unified data model for Vivado, from Register-Transfer Level (RTL) logic, to finished, placed and routed designs. According to Ramine Roane, Director of Product Marketing at Xilinx, this enables a consistent reporting capability as users sequence through the flow, utilizing progressively more refined timing, power, and interconnect models. The unified data model also enables cross-probing across levels of abstraction to design source files.

Roane says that Vivado has the capacity to handle designs as large as 100M+ equivalent gates (more than 10M look-up tables or LUTs). The Vivado IP integrator provides a drag and drop Graphical User Interface (GUI), which designers can use to automatically interconnect IP from multiple sources in the IP-XACT format. Changes to the properties of interconnected modules, such as bus width, are automatically propagated to connected blocks by the Vivado IP Integrator tool.

Vivado supports Xilinx's 2.5D IC with Stacked Silicon Interconnect (SSI, i.e. a silicon interposer), the Virtex-7 2000T. According to Roane, all SSI customers are already using Vivado, which will take into account the routing delay through the interposer when performing place and route across die slices.

Adopting ASIC Place & Route Optimization Algorithms

Based on lessons learned from the Application-Specific Integrated Circuit (ASIC) world, Xilinx has updated the placement and routing optimization algorithms in Vivado from the simulated annealing techniques that have commonly been used in FPGAs. Vivado employs analytical optimization techniques for deterministic place and route, which utilize more complex multi-variate optimization algorithms to take into account global design parameters, such as total wire length. According to Roane, simulated annealing ran out of gas at 40nm, since such algorithms are limited to local random movements in optimizing a placement.

Vivado also incorporates Xilinx's clock-gating methodology, which allows entire slices of an FPGA, consisting of eight flip-flops and four 6-input LUTs, to be shutoff during idle periods. Designers will be able to choose specific clock groups or modules where they wish to use clock-gating power optimization. The Vivado power analysis tool will then report estimates of power consumption in the modules or clock groups. Vivado power analysis can be performed post-synthesis, or post- place and route. Vivado uses its internal simulator to estimate the toggle rate of flip-flops, to calculate estimated power.

Regarding the details of Vivado's power estimation algorithm, Xilinx provided this update:

Vivado supports Switching Activity Interchange Format (SAIF) and Value Change Dump (VCD) format to pre-populate toggle rates, or it can estimate them in a “vector-less” mode, using the logic within the netlist. Unified Power Format (UPF) is not supported at this point. The power algorithm infers clock enables for groups of sequential elements, with the goal of minimizing dynamic power with no more than a 1% utilization increase.

Vivado Place and Route supports an "out-of-context" design flow, which allows designers to implement complete sub-modules independently in a hierarchical methodology, and connect with the top level of the design after the block is finished.

Users can employ the Vivado graphical editor to modify physical placement and routing, or utilize TCL scripts. Xilinx has enabled a TCL interface to Vivado for traversing and analyzing a design, as well as for performing modifications. Roane says that Xilinx anticipates developing a community of users, who will share TCL scripts and best-practices, for possible inclusion in future versions of the tools.

Vivado ESL Design and Simulation

Vivado integrates the AutoESL C-to-RTL (VHDL or Verilog) synthesis tool, which Xilinx acquired in 2011, and will now be called Vivado HLS. Users can perform direct simulation of C-language, C++ models, or System-C in Vivado HLS. Xilinx has enhanced the performance of their Verilog and VHDL mixed-language simulator - ISim,  by 3X says Roane. New features will support simulation with C-models, and co-simulation with hardware for FPGA in the loop acceleration. By choosing blocks that have little interaction with the rest of the design, users can experience simulations speedup of up to 100X with FPGA in the loop, according to Roane. Xilinx is planning to release the hardware acceleration feature later this year.

Roane says that  AMS blocks would be good candidates for hardware co-simulation, and he also anticipates the feature to be widely used with the Zynq processor platforms. Designers could run their software on the actual Zynq ARM Cortex-A9 cores, and link to Verilog or VHDL simulation of the FPGA fabric.

Hardware/Software Co-Design in Vivado?

While designers will benefit from Vivado's hardware co-simulation of the ARM processing system and FPGA logic in Zynq, further enhancements will be needed to guide designers toward an optimal partitioning of hardware and software. Vivado HLS can convert C to RTL, but designers are left to discover on their own which portions of software would most benefit from hardware acceleration. Vivado HLS synthesis and  C-simulator does support rapid exploration of the possible benefits of parallelizing C functions in the first release.

Roane says that Xilinx is working on profiling tools, to help guide software engineers to find which functions could benefit from implementation in the FPGA fabric. He makes a point to emphasize that Vivado is not intended for use by software developers. It is targeted at speeding up the design process for RTL designers, who have implemented portions of their design in higher-level languages.

Price and Availability

Xilinx says that they engaged with more than 100 beta customers in the development of Vivado, and have partnered with more than 20 IP and EDA companies to prepare for the Vivado launch. The Vivado Design Suite version 2012.1 is currently available as part of an early access program. Xilinx is targeting a general release with version 2012.2 early this summer, followed by WebPACK and Zynq-7000 EPP support later in the year. 

The company says that ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to IDS at no additional cost. Xilinx will continue to support ISE for customers targeting 7 series devices and prior generations.

DSP synthesis startup Algotochip emerges from stealth mode

Algotochip claims to be able to create DSP designs directly from C-language algorithm descriptions.

Algotochip, a Silicon Valley-based startup focused on the synthesis of Digital Signal Processor (DSP) Systems on a Chip (SoCs) directly from C-language algorithms, emerged from stealth mode at the GlobalPress Electronics Summit in Santa Cruz, CA today.


In his presentation, Algotochip CTO Satish Padmanabhan acknowledged that the long-held notion of an ESL tool that could synthesize an entire system written in 'C' is not realistic. However, by constraining their solution to sequential processes for executing DSP algorithms, Algotochip can directly realize a system and generate all aspects of the solution, including the software, firmware, and the Register-Transfer Level (RTL) description and GDSII physical layout.


Padmanabhan said that he does not classify his company as an Electronic Design Automation (EDA) provider, but as an R&D partner for his customers. The customer does not need to use nor need to have any knowledge of Algotochip's proprietary technology and tools. Customers just provide a textual system specification, and the executable C-language algorithm, along with a set of test vectors as inputs to the Algotochip process.

Algotochip then works with the customer to understand the functions of their algorithm, perform the necessary optimizations, and then generate a design for the target implementation that is 100% license free and owned by the customer.


The synthesized design includes a Software Developer Kit (SDK), which includes a compiler, assembler, linker and a cycle-accurate simulator. Algotochip also provides the necessary firmware, and hardware, including the architecture with synthesizable RTL and  physical implementation in GDSII format. According to Padmanabhan, the entire process can be completed in just 8-16 weeks.


For DSP designs, he said that the methodology can automatically determine the parallelization that is required to execute the algorithm in hardware. The tools will determine where the hardware-software partitioning calls for insertion of hardware accelerators, such as LTE Turbo encoding, versus synthesis of a programmable processor for less performance-intensive tasks. However, the target platforms for Algotochip's solution are currently limited to ASIC implementation. Algotochip is working on a solution for FPGAs, says Padmanabhan.


As part of the announcement at the GlobalPress summit, Algotochip announced that they had delivered a SoC silicon solution to LTE PHY and protocol stack provider mimoOn, for their mi!MobilePHY reference chain. The companies say that the design process, with generation of complete SoC GDSII for mimoOn’s C-code, was completed in 12 weeks, for TSMC90GOD and TSMC40G processes.


Padmanabhan, who was the Chief Architect of 10Gigabit Ethernet and 10Gigabit SONET products at Riverstone Networks and Lucent Technologies, says that Algotochip has been funded by the venture arm of a "large corporation". He expects that the investor's identity will be revealed "in the next 2 or 3 months".

Nokia gives away 16,000 Windows phones, as Moody's downgrades credit rating.

Nokia CEO Stephen Elop introduced the Lumia 900
Windows Phone at the 2012 Consumer Electronics Show

At a meeting of the Silicon Valley chapter of the Mobile Monday Group, on April 16, Nokia's Windows Phone evangelist boasted that the company has given away more than 16,000 Windows phones, in its attempt to catch up with the vast ecosystem of application developers that rivals Apple and Google possess.

Nokia continues to struggle in its shift to an alliance with Microsoft for the Windows phone platform, and after announcing lower expectations for Q1 financial performance, Moody's lowered the company's credit rating to Baa3/P-3 with a negative outlook. To make matters worse, interest in the new Lumia phones from Nokia's home base in Europe is lackluster. According to Reuters, four "major telecom operators in Europe" say that the new Nokia Lumia smartphones are not good enough to compete with the iPhone or Samsung's Galaxy Android phones.

Nevertheless, at the Mobile Monday event - which was sponsored by Nokia, GetJar's Mario Tapia showed that a poll of meeting registrants indicated growing support for the Windows Phone, which came in a distant 3rd choice to Apple's iOS and Google's Android. Biased as it was by the event being specifically about (and conducted by) Nokia for the Windows Phone, this was bad news for RIM, which received only half the votes of support of the Microsoft operating system. RIM has also tried the device giveaway ploy, distributing free BlackBerry Playbooks to all attendees at their developer conference last year.

Nokia is taking the additional step of offering a "bounty" to developers. The company will be publishing a list, which they describe as "the most wanted apps for Nokia Lumia devices and the Windows Phone platform". In a series of events at various cities throughout North America,  Nokia will be offering cash and prizes to developers for coding and delivering the desired applications.

Flashy videos provided the Mobile Monday evening's entertainment, from Nokia as well as some of the companies that were featured on-stage to demonstrate their applications. A video recording of the entire event is embedded below (with commercials if you are not a paid Ustream account holder). Since the recording is more than an hour long, and low resolution, you can go directly to Nokia's "better than sliced bread" video at the link.

The showcase of Windows Phone applications achieved very mixed results. Ebay began by showing off how they used the Metro tile interface, to input a series of progressively refined search qualifiers, in order to find an item to purchase from the Ebay site.

Greek app developer Parking Defenders followed, and preceded their demo with an animated superhero cartoon. Perhaps this was meant to distract from the the ill-conceived app itself. The notion of Parking Defender is that users will connect through the app to create an exchange system for public parking spaces. In a manner similar to FourSquare, users will be rewarded each time they check in to offer their parking spot. Users register the location (and details on the model) of their vehicle, and select the time when they plan to leave their parking spot. Other Parking Defender users in the vicinity can search for an offered spot, and the app then facilitates an exchange, including tracking of the searcher's location until the proposed swap is completed.

The notion that users would provide their personal location to strangers, along with the identity and location of their vehicle, as they approach with keys (and possibly shopping bags or other valuables) in hand, is incredibly naive. Perhaps there is no concern for personal safety or carjacking in Greece, and everyone is just occupied with the financial crisis.  On the search side of the transaction, it is not clear if the app developers are aware of laws in the majority of U.S. states that ban cell phone use while driving.

Regardless, public parking spots are just that.. public, so offering to trade one as if it was a personal possession is problematic, not to mention dangerous. It is doubtful that anyone who has witnessed a conflict over a parking spot would volunteer to make themselves a "Parking Defender", and put themselves in the precarious position to mediate between users and non-users of the app, who have the right to any available parking spot. We asked the CTO of Parking Defender about some of these concerns, and his response was "we don't promise spots, we are (just) handling information".

In order to lure consumers to purchase a Windows Phone, Microsoft and Nokia will need to do much better than this. Smartphone buyers already have more apps available than they could ever possibly use, on the iOS and Android platforms. The new Metro UI does not, on its own, convey any significant new functionality. Microsoft and Nokia would do better to focus on making the most popular apps from Android and iOS available on their new platform, so that consumers can more seamlessly move over if they choose to do so. A bounty list is not required. It's far past the time to catch up for Nokia and Microsoft, and the clock is ticking.

Related articles

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CEVA introduces 4th generation TeakLite DSP architecture for advanced audio and voice applications

CEVA's TeakLite-4 is the company's 4th generation DSP architecture, optimized for voice and High-Definition audio applications.

CEVA, Inc., licensor of Silicon Intellectual Property (SIP) DSP cores, has announced development of TeakLite-4, the company's 4th generation DSP architecture for audio and voice applications, and the 2nd generation of the company's 32-bit architecture. Moshe Sheier, Product Manager for Voice and Audio Solutions at CEVA, says that TeakLite-4 is capable of reducing power by up to 30% from TeakLite-III, due to incorporation of the latest version of CEVA's Power Scaling Unit (PSU 2.0), which the company introduced in the XC4000 architecture for wireless baseband applications earlier this year.

CEVA will initially offer TeakLite-4 in four different configurations, starting with the low-power TL410/411 in Q2, which are targeted for integration in standalone DSP chips. The smallest device in the family, the TL410, is 25% smaller than TeakLite-III, says Sheier, utilizing a less than 100K gate core. The TL410 incorporates a single 32x32-bit Multiplier-Accumulator (MAC), and the TL411 (140K gates) provides dual 32x32-bit MACs. Both versions of TeakLite-4 incorporate a 64-bit data memory bandwidth interface for local DSP memory.

The high-performance CEVA TL420/421 (190K/230K gates), which will be available in Q3, are targeted for integration in heterogeneous application processors, combining DSP with a CPU. Targeted markets are for mobile, Digital TV (DTV), and Set-Top Box (STB) applications. The TL420/421 provide similar choices of single or dual 32x32b MACs, with the addition of an optional memory subsystem for interfacing to cache controllers, and a master/slave ARM Advanced eXtensible Interface (AXI). In a TSMC 28nm HPM process, the TeakLite-4 can operate with up to a 1.5GHz clock frequency.

Sheier says that CEVA customers can optimize the TeakLite-4 DSP architecture for their requirements, choosing either one, two, or four 32x32-bit MACs, or two or four 16x16-bit MACs, and an optional Floating Point Unit (FPU).  For high performance applications, such as in High Definition audio codecs, and wideband voice and audio post-processing, TeakLite-4 can execute up to four 32x32-bit (or 16x16-bit) MAC operations per cycle. CEVA also supports 16x32 or 24x24-bit operations.

Customers can differentiate their end products by adding their own accelerators, and by adding their own extensions to CEVA's audio/voice optimized Instruction Set Architecture (ISA). Users can also employ optional ISA components, such as CEVA's bit-stream processing acceleration.

Related article

• CEVA announces new DSP cores with reference architectures for LTE-Advanced, 802.11ac WiFi.
• CEVA adds GPS capability for XC series communications processors

ARM announces Cortex big.LITTLE physical IP optimized for TSMC 28nm processes

ARM Processor Optimization Packs provide augment a library of physical IP with benchmark reports and
documentation of ARM's implementation knowledge, to accelerate design with the Cortex A-series cores.

Semiconductor intellectual property provider ARM has announced availability of Processor Optimization Packs (POPs) for TSMC 40nm and 28nm processes, in nine new configurations for the Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores.

POPs provide ARM licensees with Artisan Physical IP logic libraries and memory instances, which ARM has tuned for use with a given A-series processor core and fabrication technology. John Heinlein, Vice President of Marketing in the Physical IP Division at ARM, says that POPs are typically targeted to high-performance applications. Hence, the POPs are based on ARM's larger, higher performance 12 track libraries, though occasionally lower power-optimized 9-track libraries are used. The optimizations which ARM performs are focused on the processor and cache controller, looking at the logic, high speed memory path, and all the performance-critical aspects.

Heinlein says that ARM's Physical IP development engineers closely collaborate with ARM processor engineers, in an iterative process, to identify the optimal results for each POP. When the optimizations are complete, the engineers produce benchmarking reports that document the exact conditions and results that they achieved for the core implementation.The benchmark reports become the second set of deliverables with the POP.  

Also included with each POP is an implementation guide, which details the methodology that ARM used to achieve their results, so that ARM's end customers can achieve the same implementation quickly and at low risk.  The implementation guide is derived from a full physical implementation, and includes information on the critical paths, the layout floor plan, and a set of synthesis, place and route guidelines. While ARM does not prescribe a specific implementation flow, according to Heinlein, they do work with each of the major EDA vendors to make sure that POPs work in their flows.

ARM does not actually tape out the POPs directly, but they do fabricate test chips, which provide verification points on individual IP.  The benchmark reports which ARM delivers in a POP are based on simulations of the fully populated GDS-II layout database, says Heinlein.

To date, ARM has 28 POP licensees, according to Heinlein. He says that approximately 50% of core licensees also license the POPs, with a mix of new and existing customers. Customer who are new to ARM IP licensing will often choose POPs, since they know they have a long learning curve, which they hope the POP  will accelerate. On the other hand, existing customers have already experienced the difficulty of optimizing their designs, so they find it valuable to license the POP when they see the results ARM has achieved.

ARM's new POP announcement is for the TSMC 28nm High Performance for Mobile (HPM) and 28nm High Performance (HP) processes. ARM is launching new POPs for the previous generation Cortex-A9 core, and also the first POPs for their newest Cortex-A7 and Cortex-A15 processors. The A7 and A15 cores together are the basis for ARM’s big.LITTLE solution for power efficient multicore design. ARM says that their lead licensee for the Cortex-A15 TSMC 28nm HPM POP is expected to tape out of its first chip in the next few months.

In addition, ARM is adding their new new Cortex-A7 POP for the TSMC 40nm Low Power (LP) process, to their existing 40nm POPs for the Cortex-A5 and Cortex-A9 processors. ARM says they are also working with TSMC to develop new POP variants for the latest high-speed options in the 40nm LP process.

Related articles

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Intel announces OakTrail based Studybook tablet for education market

The Intel Studybook is built in a shock-resistant plastic case, with I/O port
covers to protect against liquids and dust, and support for front and rear cameras.

Intel Corporation has introduced a new Atom Z650-based (Oak Trail) tablet computer, the Studybook, as an addition to the company's Learning Series family of products. The Studybook tablet is a ruggedized design intended for classroom use by young children. Intel says that the Studybook can withstand accidental drops from a standard student desk and is also water- and dust- resistant, built from a single piece of plastic with shock-absorbers around the screen. Pricing will be set by Intel's OEMs and ODMs, but Intel says that they anticipate Studybooks to be offered in the $199-$299 US price range.

Intel will provide specialized educational software for the Studybooks, including classroom management, LabCam applications that support scientific enquiry, and an optimized e-reader. Intel also includes software to facilitate teacher-student collaboration in the classroom.

The Studybook prototype system configuration includes optional front (0.3Mpx) and rear (2.0Mpx) cameras, a microphone, and a 7-inch, 1024x600 capacitive multi-touch LCD screen. The Studybook application processor is the 1.2GHz version (Z650 vs. 1.5GHz - Z670) of the older generation 45nm Atom Oak Trail, the predecessor to the 32nm Medfield processor which Intel is deploying in their recently announced smartphones. Operating system support includes Microsoft Windows 7, and Android.  Standard connectivity is 802.11b/g/n WiFi, with optional 3G and Bluetooth support.

Intel expects partners to announce availability in the next few weeks.

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Intel and Xilinx invest in EDA startup Oasys Design Systems

Electronic Design Automation (EDA) startup Oasys Design System has announced that they have closed a Series-B round of funding, with investments from Intel Capital and Xilinx Technology Ventures. Oasys, which made its debut at the 2009 Design Automation Conference, produces the RealTime Designer tool for physical implementation of chip designs from Register Transfer Level (RTL) descriptions.

Though the size of the funding round has not been disclosed by Oasys, Xilinx states that the size of their investments are typically $1M to $3m. Xilinx has previously listed Oasys as one of the active investments of their Technology Ventures arm, in conjunction with their multi-year licensing agreement for  Real Time, which the two companies announced in June, 2010.

Oasys has attracted attention in EDA circles by luring former Cadence CEO Joe Costello back into the industry as a board member and investor, after a failed attempt with analog synthesis startup Barcelona Design. Former Synopsys executive Sanjay Kaul also was an early investor, and acted as Executive Chairman for Oasys.

Cisco puts LAN control in the cloud, with apps for new Linksys WiFi routers.

With the introduction of their new family of Linksys EA Series WiFi Routers (EA4500, EA3500 and EA2700), Cisco has also announced they will be making their home network management Connect Software available for users to access in the cloud. Linksys router owners will be able to log into their Cisco Connect Cloud account from a web browser, or by installing the Cisco Connect Express application for use on Android and Apple iOS devices.

Connect Express allows users to give guests Internet access on their home wireless local area network (WLAN), set parental controls, and add devices to their network remotely through Cisco Connect Cloud. Cisco plans to extend the Connect Cloud application for control of other home connected devices, and announced that they are working with Whirlpool and "more than two dozen other industry-leading companies, app developers and service providers" on the connected home strategy.

The three new 802.11n WiFi routers range from the Linksys EA2700 Dual-Band Router ($99) with four Gigabit Ethernet ports, to the EA3500, which adds a USB port ($139), to the top of the line EA4500 ($199) with Digital Living Network Alliance (DLNA) Media Server support. Cisco specifies that all three routers are IPv6 compatible. 

By pairing the EA4500 router with 3X3 adapters in both the 2.4GHz and 5.0GHz band, Cisco says that users can achieve up to 900Mbps data transfer speeds (i.e. up to 450 Mbps for each band). Cisco's maximum performance specification for the EA3500 is 750Mbps, and 600Mbps for the EA2700, also in dual-band 3X3 operation.

Android U.S. market share growing twice as fast as Apple's

Top Smartphone Platforms 3 Month Avg. Ending Feb. 2012 vs. 3 Month Avg. Ending Nov. 2011 Total U.S. Smartphone Subscribers Ages 13+ Source: comScore MobiLens
	Share (%) of Smartphone Subscribers
	Nov-11	Feb-12	Point Change
Total Smartphone Subscribers	100.0%	100.0%	N/A
Google	46.9%	50.1%	3.2
Apple	28.7%	30.2%	1.5
RIM	16.6%	13.4%	-3.2
Microsoft	5.2%	3.9%	-1.3
Symbian	1.5%	1.5%	0.0

The numbers in the chart above come from comScore's February 2012 U.S. Mobile Subscriber Market Share report. For the study, comScore states that they surveyed more than 30,000 U.S. mobile subscribers. The report also compiles data that shows, as of the end of February, 2012, more than 104 million people in the U.S. now own smartphones. This represents 14% growth in the three months since the last comScore report, at the end of November, 2011.

According to comScore's data, Android smartphone market share grew to 50.1% in February, an increase of 17% over the last year. Apple's iPhones grew share by just 5% over the same period, now accounting for 30.2% of the U.S. smartphone market, according to comScore. RIM and Microsoft continue to lose market share, down by 3.2% and 1.3%, respectively.

These results are interesting to compare to some highly publicized reports last July, which claimed that Android had peaked in March 2011 (see Android's lead over iOS. Whose numbers should you believe?).  Several reports last summer also claimed that Android users would be joining RIM Blackberry users in switching to iPhones. While comScore's data clearly shows that Android growth has not peaked, digging further into the numbers we also find that there is no evidence of massive Android-to-Apple exchanges. In fact, we see that Blackberry users are switching to Android by a nearly 2-to-1 margin.

This table presents a more detailed analysis of the comScore numbers. At a 14% growth rate, the total number of U.S. smartphone users increased by 12.8M, from 91.2M units in November-2011, to 104M units at the end of February 2012. Adoption of the iPhone increased by 5.2M units in the U.S. over this 3-month period, while Android users increased by 9.3M. Taken together, RIM and Microsoft lost 1.9M users. 

If we assume that the 1.9M users that Blackberry and Microsoft lost switched to other smartphones, we can see that the total market growth available to Apple and Google was actually 14.7M units. The comScore data shows that Google and and Apple captured nearly 99% of the total growth, accounting for 14.5M units between the two companies. Google captured 63.5% of the total market growth, nearly doubling the growth that Apple achieved.

Far from taking over the market, this analysis shows that Apple is lagging behind Google in picking up new users as they switch off of older smartphone platforms. One factor could be the lack of a physical keyboard on the iPhone, inhibiting Blackberry users who are more likely to not have made the switch to a touch screen user interface. Those users can move to a device such as Motorola's DROID Pro, which provides a very familiar look and feel for Blackberry users.

Redpine introduces 5GHz WiFi tags for Real-Time Location Systems

WiFi-based Real-Time Location Systems (RTLS) utilize a combination of active RF tags and access points to track the location of materials, equipment, or even personnel within a known, controlled environment. Common applications are in warehouses or shipping facilities, secure buildings, and hospitals. RTLS application software is added to servers connected with standard Wireless Local Area Network (WLAN) infrastructure, utilizing methods such as triangulation and calculation of signal strength to determine a tag location. Accuracy of location can be enhanced by equipping the tags with built-in motion sensors. Sensors can also be added to RTS tags for triggering of alarm signals.

Wireless chipset vendor Redpine Signals has introduced a new WiseMote WM1-50 RTLS tag, which Redpine CEO Venkat Mattela says is the first in the industry to offer dual 2.4/5 GHz 802.11n WiFi operation. According to Mattela, thought it may be counter-intuitive, 5GHz operation can actually provide a significant power savings compared to 2.4GHz WiFi. The reason is that there are only three channels available in the 2.4Ghz IEEE-802.11n standard, while there are twenty in the 5GHz band. The tags typically operate with long periods in low power sleep mode, waking up briefly to communicate with the network. When there is a lot of traffic on the more crowded 2.4GHz band, the active period of the tag is extended, consuming more battery power. 

Block diagram for a Redpine SIgnals WiseMote RTLS tag

Redpine says that the WM1-50 RTLS tag supports a variety of location tracking and update schemes, including configurable beacon patterns compliant with Cisco Compatible Extensions (CCX) specifications for WLAN client devices. The companion WM0 Configurator device from Redpine enables the the tags to be configured wirelessly through low frequency signaling when they are brought into proximity. The WM0 uses a USB connection to communicate with a controlling PC.  Configuration information is exchanged directly between the tags and the WM0 over WiFi, without the need to connect to the WiFi infrastructure. Redpine provides customers with a Software Developer Kit (SDK), sample applications and APIs for integration of the tags and Configurator with custom location engines.

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