Synopsys speeds up protocol verification for SOC communication interfaces

The new Synopsys VIPER architecture is a protocol-centric system
for verification of communication interfaces on SOCs

Synopsys Inc. has announced a new set of tools in their family of Discovery Verification Intellectual Property (VIP) products, focused on analysis and debug of communication protocols such as Universal Serial Bus (USB), Double Data Rate (DDR) memory interfaces, and Peripheral Component Interconnect Express (PCIe).

Neill Mullinger, Group Marketing Manager for VIP at Synopsys, says that the company has written the new library entirely in SystemVerilog, based on an architecture they have dubbed "VIPER", with native support for the industry-standards: Universal Verification Methodology (UVM), Verification Methodology Manual (VMM) and Open Verification Methodology (OVM). Mullinger says that by writing the new VIP family completely in System Verilog, the same language which verification engineers are typically using for their testbenches, the inefficiencies and overhead associated with plugging in legacy VIP written in 'e', VERA, or C-language models can be eliminated.

By incorporating a higher-level class library, Synopsys has architected the VIP so that users can compile just what they need for their chosen methodology, without carrying the overhead of extraneous components, says Mullinger.  To make the VIP easier to use, Synopsys provides built-in test plans with "Quick Start" instructions in Hyper Text Markup Language (HTML) form, which guide verification engineers on how to configure the VIP for their tests.

Synopsys Protocol Analyzer highlights bottlenecks or errors in a communication interface

To make the VIP easier to debug, Synopsys has also developed a Protocol Analyzer, a Java-based tool that the company designed with an awareness of the verification requirements for various communication protocols. Hooks are built into the VIP so that users can easily monitor signals with the Protocol Analyzer. Users can monitor activity in a communication interface on a transaction by transaction basis, highlighting the relationships of data transfers, packets, and handshaking across the protocol hierarchy. Tests of multiple protocols can be graphically linked to synchronize display of data communication across an interface. Since the data for the Protocol Analyzer is generated directly by the VIP, Mullinger says that all major simulators are supported.

Synopsys has enhanced their portfolio of VIP through their recent acquisitions of nSys Design Systems, and ExpertIO, and includes USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, OCP. For a  complete list see http://www.synopsys.com/VIP/.  The video embedded below provides Synopsys' introduction to the new Discovery VIP, from several of the company's R&D and marketing staff, and a customer testimonial from Cavium.