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| Block Diagram for Freescale's T4240 multicore processor |
Freescale Semiconductor has announced that their 28nm T4240 embedded multicore processor, which features 24 virtual cores for high-end data plane processing applications, has achieved the highest CoreMark benchmark performance score ever recorded for an embedded processor, in emulator tests performed by the company. In the tests, Freescale ran their 12-core T4240 model at 1.8GHz, achieving a 1.4X improvement in CoreMark/Watt versus a competitor's 1.5GHz, 32-core processor. The improvement over a dual 6-core server blade, running at 2.266GHz, was 3X.
Freescale is targeting the device for service providers in wireless backhaul, enterprise and defense applications. According to Freescale, the T4240 will deliver 4X the performance and 2X the power efficiency over Freescale's current generation 8-core P4080, for both core processing and data throughput.
Freescale is targeting the device for service providers in wireless backhaul, enterprise and defense applications. According to Freescale, the T4240 will deliver 4X the performance and 2X the power efficiency over Freescale's current generation 8-core P4080, for both core processing and data throughput.
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| The T4240 and T4160 employ clusters of 4 e6500Power Architecture cores. |
The T4240 employs the new multithreaded, 64-bit Power Architecture e6500 core, which Freescale announced for their QorIQ Advanced Multiprocessing (AMP) series at their Technology Forum in June, 2011.The e6500 incorporates an enhanced version of the AltiVec vector processor, a 128b SIMD (single-instruction multiple data) unit that operates independently of the scalar processor and FPU (floating point unit), at up to a 2.5GHz clock rate. Freescale uses the AltiVec technology to address high-bandwidth data processing and algorithmic-intensive computations.
Freescale's architecture groups the cores in clusters of four e6500s. Each core has its own L1 cache, and a 2MB L2 cache is shared among the four cores in each cluster. An individual core also sees the L2 from the other clusters, along with 512KB blocks of Platform Cache connected through the CoreNet, as a large L3 cache. The 40b physical address bus can access up to 1TB of external memory. The T4240 integrates three e6500 clusters, while a new T4160 employs two clusters.
Networking features of the T4240 include 50Gbps of packet parse, classify and distribute acceleration, 32-10G Serdes lanes, and four 10GbE MACs. The T4160 has 24-10G Serdes lanes, and two 10GbE MACs. New features include a 20Gbps Data Compression Engine (DCE), a regular expression pattern matching engine for application recognition and data loss prevention, and new functions to support Data Center Bridging (DCB) or lossless ethernet. System interconnect technologies include PCIe rev 3.0 with Single Root I/O Virtualization (SR-IOV) to facilitate high speed peripheral expansion.
Networking features of the T4240 include 50Gbps of packet parse, classify and distribute acceleration, 32-10G Serdes lanes, and four 10GbE MACs. The T4160 has 24-10G Serdes lanes, and two 10GbE MACs. New features include a 20Gbps Data Compression Engine (DCE), a regular expression pattern matching engine for application recognition and data loss prevention, and new functions to support Data Center Bridging (DCB) or lossless ethernet. System interconnect technologies include PCIe rev 3.0 with Single Root I/O Virtualization (SR-IOV) to facilitate high speed peripheral expansion.
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| The Queue Manager in the T4240 and T4160 performs load balancing and SoC-level power management. |
Freescale specifies the power for the T4240 at 30W, and 25W for the T4160. To manage power, Freescale has made extensive use of dynamic clock and power gating - which they call a "drowsy" mode - at the core, cluster, and whole SoC level. Users can put the AltiVec processor into drowsy mode separately from the e6500 core, for applications where it is not being used at all, or on an individual core. State retention registers enable fast recovery from the core drowsy mode, within 200nSec after an interrupt is received. A Queue Manager (QMan), which can manage up to 224 queues, performs load balancing and what Freescale refers to as Cascading Power Management, across the entire SoC.
Freescale is working with Advantech on a T4240 Advanced Telecommunications Computing Architecture (ATCA) development system platform for wired and wireless service provider applications in the Telecom industry.They are working with other partners on a VPX development system for aerospace and defense, and a Peripheral Component Interconnect Express (PCIe) version for datacenters. Freescale is planning to start sampling for the T4240 and T4160 in mid-2012.
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