Cavium Networks is a 10-year old provider of MIPS® and ARM®-based SOCs (systems on a chip) for networking, communications, storage, video and security applications. The company moved to its new headquarters in San Jose, CA today.
Earlier this year, Cavium acquired 4G baseband DSP (digital signal processor) provider Wavesat, and in November 2009, they acquired embedded Linux developer Montavista. YJ Kim, General Manager of the Infrastructure Processor Group at Cavium, delivered a presentation on the company's 4G mobile infrastructure solutions at the recent Linley Tech Carrier Conference. Cavium has designed a family of MIPS-64 based processors for 4G (4th generation) base stations, RNC (radio network control), and core network applications. The latest generation OCTEON II ranges from a single-core device to a 32-core SoC.
Kim began by describing the complexity challenges for 4G network processors. In LTE (long-term evolution) infrastructure. The E-UTRAN (Evolved Universal Terrestrial Radio Access Network) base station, eNodeB or eNB, takes on added complexity over 3G (3rd generation) since the eNB also integrates the RNC (radio network control) functions. LTE promises a 10X or greater increases in data rate over 3G networks, but base station radios must live within a 15W to 20W power budget. All-IP networks will utilize security and DPI (deep packet inspection) functions, such as the 3GPP use of the SNOW 3G algorithm, with the result being up to a 40Gbps/Blade data throughput requirement in core network processing, according to Kim.
The OCTEON II CN66XX integrates 6-10 MIPS64 v2 cores for 3G/4G/LTE wireless base stations. |
For Layer-2 to Layer-7 (MAC/Scheduler/Control/Transport) processing in LTE base stations, Cavium starts with the 2-4 core CN62XX design, which integrates 2-4 MIPS cores that are capable of operating at a 1.0 GHz clock rate. The next step up is the CN63XX family, which offer 2-6 MIPS cores while increasing operating speed to 1.5GHz. Cavium targets the OCTEON II CN66XX family at high performance 3G/4G/LTE wireless base station platforms, with 6-10 1.5GHz MIPS cores. The CN66XX provide a 2MB L2 cache, DDR3 (double data-rate) memory controller, hardware acceleration for the SNOW 3G and KASUMI security algorithms, TCP/IP (Transmission Control Protocol/Internet Protocol) packet processing acceleration, and QoS (quality of service). Cavium's PowerOptimizer™ technology limits maximum power from 9 to 20 watts from low-end to high-end configurations.
The CN66XX SoC also includes several SERDES (serializer/deserializer) I/O’s for PCI-e (Peripheral Component Interconnect express) Gen2, XAUI (10 Gigabit Attachment Unit Interface), and SRIO (Serial RapidIO). Users can take advantage of the integrated HFA (Hyper Finite Automata) DPI engine to perform deep packet inspection. Cavium also integrates accelerators for data compression, and encryption/decryption. The "Acclr" (application accelerator) manager engine is a hardware load balancer that distributes packet and control processing to the embedded cores, in a similar fashion to the ARM-based dispatcher in the Mindspeed Transcede base station SoC.
Authentik™ is Cavium's anti-counterfeiting technology. With Authentik™, OEMs (original equipment manufacturers) can lock the multi-core processing chip, so that third parties can assemble their systems while reducing the risk that counterfeit copies of the system can be created. The CN66XX is software compatible with the OCTEON 63/62XX, so that designers can scale the architecture from macro to pico cells or micro cells.
Authentik™ is Cavium's anti-counterfeiting technology. With Authentik™, OEMs (original equipment manufacturers) can lock the multi-core processing chip, so that third parties can assemble their systems while reducing the risk that counterfeit copies of the system can be created. The CN66XX is software compatible with the OCTEON 63/62XX, so that designers can scale the architecture from macro to pico cells or micro cells.
Unlike competitors that are offering "base station on a chip" SoCs, you must add an external FPGA or DSP ASIC to handle Layer-1 PHY (physical layer) functions. Cavium demonstrated such a solution at the recent Femtocell World Summit in London, by combining Picochip's PC960x LTE radio and PHY with a Cavium OCTEON processor.
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