Highlights from the Design Automation Conference, #46DAC - Day 1

I think this was my 15th Design Automation Conference (DAC), but the very 1st which I attended as an observer and not as an employee of an exhibitor company. That made it a very different experience, giving me the opportunity to partake in a much broader view of the Electronic Design Automation (EDA) industry, one that is more fitting with my current role as a technology industry analyst. Most EDA veterans will probably agree with me when I say that I really enjoyed not being tied to a booth or demo suite this time.

If you are not familiar with EDA, simply put it is an industry group which provides tools that semiconductor company engineers use to design their chips. EDA is a key component of the semiconductor ecosystem, which IBM's Dr. Juan-Antonio Carballo referred to as the "parent industry" while moderating the annual CEO panel discussion. EDA also provides tools for the before and after of IC design; for electronic system-level (ESL) architectural design and for printed-circuit board (PCB) design. There is an ongoing emphasis on moving EDA further up the chain to system level, as chip complexity increases and the core IC tools have become commoditized. For my readers who have followed my posts on the wireless industry, EDA system level tools are playing an increasingly important role in development of 4G technology.

Though many within EDA have attempted to describe an "EDA ecosystem", the true role of EDA as a supplier to the much larger electronics industry was never more evident than at the 46th Design Automation Conference. More on that later.

The official "preliminary" DAC attendee count came in at 3,247 "exhibit only", a 12% increase from last year, no doubt due to the move back to San Francisco after trips through Anaheim (2008) and San Diego (2007). That count includes the press, analysts and employees of approximately 200 exhibitor companies. The crowd seemed light in the Moscone Center, but my schedule was so full that I didn't get to see some of the companies I wanted to visit during my three days. I came away with a lot of information to process and report on, so a quick summary debrief is probably the best way to start.

Herein then are the highlights from my agenda. I will go into greater depth on the more interesting aspects as time permits. Hopefully, the breadth of this summary will provide a glimpse into just how much information there is to digest. (This post got so long that I split it up into Day 1 - Day 3).

Feel free to leave a comment on areas that you are most interested in.

Monday - Day 1

1. Gary Smith's pavilion presentation on "Trends and What’s Hot at DAC"

Gary Smith has been known as "the EDA analyst" for many years, and he traditionally kicks off DAC with his "What to See" presentation. He now works for the DAC organizers as a member of the DAC Strategy Committee, which may explain his (ineffective) attempt to lead a chant of "I Love DAC" at the beginning of the Monday morning session. It was uncomfortable to see an industry analyst acting as an industry cheerleader.

As in recent years, Gary emphasized ESL, ESL, and ESL. I counted 16 ESL companies on his "What To See" list, out of a total of 24. Indeed, the need for advances in System on a Chip (SoC) design flows was a recurring theme at the show.

2. TSMC Open Innovation Platform Theater

Open Innovation is a major push from TSMC, showing that the days of proprietary formats for EDA tools may finally be coming to an end in the foundry design flows. The TSMC booth was a convenient place to stop and get a quick presentation from members of the TSMC Open Innovation Forum.

3. Jim Hogan's panel of "Hogan’s Heroes: The Long Road to System-Level Sign-Off"

Jim's panel included Grant Pierce, CEO of Sonics, Steve Leibson - Technology and Marketing Consultant, Peter Levin - Dept. of Veterans Affairs (former CEO of DAFCA). Continuing the ESL theme, Jim highlighted how SoCs are more difficult than ever to design because of the "big change" to heterogeneous multiprocessor architectures.

Panelist comments:

• Need integrated communication standards. Must be driven by smaller companies.
  
• Standards needed, at the "right" level of abstraction.
• How can we "capture the application"?
• What about reliability? Reliability definition depends on willingness to pay.
  
• 'C'-language models lack timing information, and can't detect manufacturing faults.
• Variability becomes more of an issue, which system design tools currently don't handle.
• Virtual platforms are of increasing importance. Must develop software with the possibility of multiple hardware implementations.
• No one company can do it, need a "virtual" corporation".
• How to make money in ESL?
  

4. The Atrenta-sponsored "blogfest" on "Early Design Closure: Is sooner really better?"

Panelists were; Jim Hogan - EDA angel investor and industry mover and shaker, Mike Fazeli - Atrenta VP of Strategic Development, and Bernard Murphy - CTO at Atrenta.

This was an interesting new experiment by Atrenta, which recognized the rising importance of bloggers in the EDA industry. It was almost a continuation of Jim Hogan's panel in a more intimate setting, coming immediately after the pavilion panel discussion. Other participants included Paul McLellan of EDA Graffiti.

Some of the discussion points:

• SoC design is now about optimization, not features.
• Verification requires building quality in.
• Time-to-market delays and yield issues are increasing at sub-40nm process nodes, affecting time to ROI.
• More on collaboration needed; partnering of system and consumer product companies such as Apple and ARM.
• "It's not an EDA problem, it's a semiconductor problem"
• Some companies, such as Cisco, have moved to FPGAs in systems that provide margin, "software in-a-box". This requires same tools as SoC.
• Prediction for 2 DACs from now: "IP explodes", more verification required, IDMs divest.
• Changing EDA-Semiconductor relationship
  

5. Keynote Panel: "Futures for EDA: The CEO View"

Moderated by Dr. Juan-Antonio Carballo. Panelists: Aart de Geus - Synopsys, Walden C. Rhines - Mentor Graphics, Lip-Bu Tan - Cadence Design Systems.

I will have more to say about this session, which lasted more than 1:15, but here are a few bullets.

• Wally: Effect of economic downturn on EDA: 1st year of "negative growth". (Hmm.. I wonder if that describes the auto industry.. negative growth? Oh how I miss George Carlin!).
• Aart: the entire industry has to be about increase in efficiency. The entire global standard of living has lowered.
• Facing a "massive squeeze".
• What are EDA CEOs looking for? Overall cost of design is an endemic issue. What can change time-to-market? Cost of system design - need a holistic view.
• What about innovation? Investment in fabless companies is down 70%. Startups must emphasize capital efficiency, $12M per tapeout.
• What about EDA startups? Advice to address hard problems, such as system abstraction. EDA core is a mature market. Design-for-manufacturing (DFM), ESL and analog provide growth.
• An incremental philosophy has taken over in startups, reduction in hi-tech risk taking. Too many companies want increments, but are unwilling to pay for new features.
• Aart: Customer consolidation is a problem for EDA vendors; attrition and bankruptcies. Predicts we will see more later this year.
• Should EDA have a larger share of semiconductor revenues? Aart: That is a "BS" question! Must have an economic push.
• Are IP and services growing? Synopsys has increased investment in IP. There is increasing outsourcing to physical layout services.
• Could EDA move into other industries? Wally: Medical, military, and aerospace. Home power management.
• Are you running your company differently? Aart: Do whatever we can to help customers survive.
• Aart: Need more EDA talent to see multiple aspects of a problem, how to make a design flow work together. Need to grow that talent. Great opportunity.
  

Phew! That's all for now, and that is just a quick glimpse of Day 1. More later.

-Mike